As chip-to-chip input/output (I/O) rates increase to accommodate bandwidth demand, it is important that multi-gigabit links consume low power, have a small area, and are robust and easily testable. As a result, such multi-gigabit links require an efficient timing convention. A timing convention may govern when a transmitter drives symbols onto a symbol line and when they are sampled by a receiver. A timing convention may be periodic, with a new symbol driven on a signal line at regular time intervals, or aperiodic, with new symbols arriving at irregular times. In either case, a method is required to encode when the symbols arrive so that the receiver samples each symbol exactly once during its valid period. For aperiodic signals, an explicit transition, such as a stroke signal, is required to signal the arrival of each symbol. This transition is generally provided by a separate clock line that may be shared amongst several signals.
One technique to enable high aggregate bandwidths is simultaneous bi-directional (SBD) differential signaling. SBD signaling operates by transmitting bits simultaneously in both directions over a single transmission line. Bits travel in one direction on the forward-traveling wave and in the other direction on the reverse-traveling wave. The line is terminated at both ends to eliminate coupling between the two bit streams. Although, the effective pin and wire density of the signaling system can be doubled by using SBD signaling, this signaling conventional introduces a new noise source crosstalk between the forward and reverse traveling waves.
A point-to-point link may use SBD signaling to transmit data simultaneously in both directions, where a forwarded clock is provided in conjunction with the data to enable source synchronous signaling. As known to those skilled in the art, source synchronous signaling is a communications mechanism where a clock is forwarded along with the data, obviating the need for distribution of a global clock. Shared source synchronous clocking may be used to minimize clocking power per bit, reduce complexity and latency, and possibly eliminate the need for data coding with its associated bandwidth overhead.
A common alternative to source synchronous clocking is to embed a clock signal into the data using coding techniques and then extract the clock at the receiver using a clock-data recovery (CDR) circuit. This clock recovery method requires extra latency due to the need for clock-data encoding and decoding. Additional power is consumed because of the added CDR circuitry and the need to over-sample for phased detection. Conversely, source synchronous clocking bypasses the need for this real-time tracking circuitry and data coding, since a significant portion of the transmit jitter and clock phase drift are common between the clock and parallel data lines.
A timing convention of the point-to-point link may operate either according to an open loop or a closed loop. In an open loop system, the frequencies and delays associated with system timing are not subject to control. The system is designed to tolerate the worst case variation in these parameters. With closed loop timing, on the other hand, one or more system timing parameters, delays and frequencies, are actively controlled. The system measures a timing parameter, such as skew, and uses feedback control to adjust the variable parameters to reduce the skew.
Accordingly, closed loop timing can greatly decrease the timing uncertainty in a system; and hence, increase the maximum data rate. Conventionally, closed loop timing for a transceiver clock architectures of a point-to-point link generally require both a delayed lock loop (DLL) and a phased lock loop (PLL) for generation of both receiver clocks and transit clocks.